A new white paper from Anritsu outlines the PCI Express (PCIe) 6.0 standards slated for finalization by PCI-SIG in 2021. The paper covers the enhanced PCIe 6.0 technologies, such as 32 Gbaud PAM4 signaling, Forward Error Correction (FEC) and link equalization. It also provides guidelines on selecting the proper test solutions to verify PCIe 6.0 designs.
PCIe interconnect I/O technology is designed to meet the high-speed data transmission needs of emerging applications and devices such as IoT, AI, “hard drives, solid state drives, graphics cards, Wi-Fi routers, and internal ethernet connections,” according to the paper. Anritsu provides a chart illustrating how PCIe data rates have accelerated in each new generation of the technology. One of the notable changes with this year’s release is that the data rates jumped from 2019’s standard of 32.0 GT/s to 64.0 GT/s. Regarding the release of PCIe 6.0 later this year, the author says, “to address signal degradation, tighter channel and connector loss and reflections parameters have been implemented. Minor improvements in receiver and transmitter equalization have been made, as well.” The report goes on to explain how PCIe 6.0 leverages PAM4, which is a change from previous generations.
“For signal integrity engineers, verifying PCIe 6.0 designs will require high-level test solutions that can accurately measure performance to ensure compliance. While many of the tests are similar to those of previous generations, the complexity of PCIe 6.0 tests and accuracy necessary require test instruments that have distinct performance thresholds.” – Anritsu, “PCIe 6.0: Testing for a New Generation“
The paper presents the key specifications of PCIe 6.0 including metrics like data rate, latency, bandwidth inefficiency, and reliability. It notes that “the evolution to PAM4 technology, as well as other enhanced specifications under the 6.0 standards development will affect testing of I/O interfaces and systems utilizing PCIe 6.0.” The author explains the effect PAM4 will have on Bit Error Rate (BER) testing, link equalization, and the importance of Forward Error Correction (FEC). While many of these test solutions are already being used by signal integrity engineers to verify their designs, “the parameters of those measurements for PCIe 6.0, however, are much more complex due to the new standards.”
While not required by the PCIe 6.0 specification, the author explains why jitter tolerance testing (JTOL) is recommended. The paper also provides guidelines on selecting the proper test solutions to verify PCIe 6.0 designs, which includes a protocol-aware bit error rate tester (BERT) and an oscilloscope.
Download the full report to learn more about the testing processes that will allow producers of data center products and systems to have a greater confidence in their complex designs for emerging applications.